The present invention relates to digital data processing and in particular to the design and operation of communications circuit interfaces for pooling calibration resources.
The increased clock frequencies of processors and other digital data components have induced designers to increase the speeds of bus clocks in order to prevent transmission buses from becoming a bottleneck to performance. This has caused various design changes to the buses themselves. For example, a high-speed bus is typically implemented as a point-to-point link containing multiple lines in parallel, each carrying data from a single transmitting chip to a single receiving chip, in order to support operation at higher bus clock speeds.
In order to support inter-chip data transfer at high bus clock speeds, the lines of a data communications bus can be individually calibrated to compensate for these and other variations.